A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS

• Main Authors: Low, Jeremy Yung Shern, Chang, Chip Hong
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/95909; http://hdl.handle.net/10220/11327
• 機構: Nanyang Technological University

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to...