Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguratio...
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Main Authors: | , , |
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格式: | Conference or Workshop Item |
語言: | English |
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2013
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在線閱讀: | https://hdl.handle.net/10356/97946 http://hdl.handle.net/10220/12235 |
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