An efficient soft error protection scheme for MPSoC and FPGA-based verification
As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by more frequently appeared soft errors are becoming critical tasks for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiproces...
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| Main Authors: | , , |
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| 格式: | Article |
| 語言: | English |
| 出版: |
2013
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/98394 http://hdl.handle.net/10220/12463 |
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| 總結: | As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by more frequently appeared soft errors are becoming critical tasks for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiprocessor systems involve either high chip cost and area overhead or much performance degradation and energy consumption, and do not fulfill the increasing requirement of high performance and reliability. In this paper, we present a hardware-software collaborated approach to efficiently manage application execution and overcome reliability threats for Multiprocessor Systems-on-Chip (MPSoC). A hardware-based on-chip sensor network is built for soft error detection, and a software-based recovery mechanism is applied for soft error correction. This strategy only introduces trivial overhead on hardware design and much lower overhead on software control and execution, and hence performance degradation and energy consumption are greatly reduced. The hardware sensor design is verified via FPGA-based implementations, which proves the feasibility of the proposed approach. A SystemC-based cycle-accurate simulator is built to further verify the effectiveness of our technique by comparing with related techniques on several real-world applications. |
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