A look up table design with 3D bipolar RRAMs

• Main Authors: Chen, Yi-Chung, Zhang, Wei, Li, Hai
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: https://hdl.handle.net/10356/99004; http://hdl.handle.net/10220/12538
• Institution: Nanyang Technological University

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for it...