A look up table design with 3D bipolar RRAMs

• Main Authors: Chen, Yi-Chung, Zhang, Wei, Li, Hai
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Computer science and engineering
• 在線閱讀: https://hdl.handle.net/10356/99004; http://hdl.handle.net/10220/12538
• 機構: Nanyang Technological University

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for it...