Retention time characterization and optimization of logic-compatible embedded DRAM cells

• Main Authors: Do, Anh Tuan, Yi, He, Yeo, Kiat Seng, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/99047; http://hdl.handle.net/10220/12575
• Institution: Nanyang Technological University

Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present a...