Retention time characterization and optimization of logic-compatible embedded DRAM cells
Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present a...
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| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/99047 http://hdl.handle.net/10220/12575 |
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| Institution: | Nanyang Technological University |
| Language: | English |