A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes

• Main Authors: Hosseini, S. M. Ehsan, Chan, Kheong Sann, Goh, Wang Ling
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: https://hdl.handle.net/10356/99867; http://hdl.handle.net/10220/6373
• Institution: Nanyang Technological University

This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of Hardware/ Software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.