A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes

A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes

This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured...

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Main Authors: Hosseini, S. M. Ehsan, Chan, Kheong Sann, Goh, Wang Ling
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2010
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Online Access:https://hdl.handle.net/10356/99867
http://hdl.handle.net/10220/6373
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-998672020-03-07T13:24:49Z A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes Hosseini, S. M. Ehsan Chan, Kheong Sann Goh, Wang Ling School of Electrical and Electronic Engineering IEEE International Conference on Signals, Circuits and Systems (2nd : 2008 : Hammamet, Tunisia) A*STAR Data Storage Institute DRNTU::Engineering::Electrical and electronic engineering::Electronic systems This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of Hardware/ Software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values. Published version 2010-08-31T01:35:12Z 2019-12-06T20:12:37Z 2010-08-31T01:35:12Z 2019-12-06T20:12:37Z 2008 2008 Conference Paper Hosseini, S. M. E., Chan, K. S., & Goh, W. L. (2008). A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes. 2nd International Conference on Signals, Circuits and Systems: Hammamet,Tunisia, (pp.1-6). https://hdl.handle.net/10356/99867 http://hdl.handle.net/10220/6373 10.1109/ICSCS.2008.4746952 en © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 6 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Hosseini, S. M. Ehsan
Chan, Kheong Sann
Goh, Wang Ling
A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
description This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of Hardware/ Software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Hosseini, S. M. Ehsan
Chan, Kheong Sann
Goh, Wang Ling
format Conference or Workshop Item
author Hosseini, S. M. Ehsan
Chan, Kheong Sann
Goh, Wang Ling
author_sort Hosseini, S. M. Ehsan
title A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
title_short A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
title_full A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
title_fullStr A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
title_full_unstemmed A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
title_sort reconfigurable fpga implementation of an ldpc decoder for unstructured codes
publishDate 2010
url https://hdl.handle.net/10356/99867
http://hdl.handle.net/10220/6373
_version_ 1681037165329383424

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