Fast timing analysis of clock networks considering environmental uncertainty
Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verificati...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2012
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/99879 http://hdl.handle.net/10220/8563 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clock-skew by an incremental-SVD-based compact modeling assisted with adaptive sampling. Firstly, an incremental-SVD is developed to perform an efficient update of environmental uncertainties avoiding a repeated full SVD. Secondly, an adaptive sampling is presented to build accurate models to sample clock and clock-skew for generating macromodels in a wide frequency range. Experiments on a number of clock networks show that when compared to the traditional fast TBR method, our macromodeling by incremental-SVD and adaptive sampling can significantly reduce the runtime with a similar accuracy. In addition, when compared to the Krylov-subspace-based method, our macromodeling further reduces the waveform error with a similar runtime. |
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