Circuit performance and yield optimization with worst-case and Monte Carlo analyses

International Symposium on IC Technology, Systems and Applications

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Bibliographic Details
Main Authors: Lan, C.S., Wenjun, Z., Tao, K., Qing, G.
Other Authors: NATIONAL SUPERCOMPUTING RESEARCH CENTRE
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/115393
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-1153932015-01-12T12:06:46Z Circuit performance and yield optimization with worst-case and Monte Carlo analyses Lan, C.S. Wenjun, Z. Tao, K. Qing, G. NATIONAL SUPERCOMPUTING RESEARCH CENTRE International Symposium on IC Technology, Systems and Applications 7 653-655 2014-12-12T07:15:03Z 2014-12-12T07:15:03Z 1997 Conference Paper Lan, C.S.,Wenjun, Z.,Tao, K.,Qing, G. (1997). Circuit performance and yield optimization with worst-case and Monte Carlo analyses. International Symposium on IC Technology, Systems and Applications 7 : 653-655. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/115393 NOT_IN_WOS Scopus
institution National University of Singapore
building NUS Library
country Singapore
collection ScholarBank@NUS
description International Symposium on IC Technology, Systems and Applications
author2 NATIONAL SUPERCOMPUTING RESEARCH CENTRE
author_facet NATIONAL SUPERCOMPUTING RESEARCH CENTRE
Lan, C.S.
Wenjun, Z.
Tao, K.
Qing, G.
format Conference or Workshop Item
author Lan, C.S.
Wenjun, Z.
Tao, K.
Qing, G.
spellingShingle Lan, C.S.
Wenjun, Z.
Tao, K.
Qing, G.
Circuit performance and yield optimization with worst-case and Monte Carlo analyses
author_sort Lan, C.S.
title Circuit performance and yield optimization with worst-case and Monte Carlo analyses
title_short Circuit performance and yield optimization with worst-case and Monte Carlo analyses
title_full Circuit performance and yield optimization with worst-case and Monte Carlo analyses
title_fullStr Circuit performance and yield optimization with worst-case and Monte Carlo analyses
title_full_unstemmed Circuit performance and yield optimization with worst-case and Monte Carlo analyses
title_sort circuit performance and yield optimization with worst-case and monte carlo analyses
publishDate 2014
url http://scholarbank.nus.edu.sg/handle/10635/115393
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