A note on compiling FORTRAN loop kernels onto a dataflow architecture

• Main Authors: Walker, E., Morgan, G., Cass, B., Ulanowski, Z.
• Other Authors: NATIONAL SUPERCOMPUTING RESEARCH CENTRE
• Format: Article
• Published: 2014
• Subjects: Dataflow architecture; FORTRAN loop kernels; FPGA devices; High performance computing; Parallelizing compiler
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/115563
• Institution: National University of Singapore

Parallel Computing