A low power design for arithmetic and logic unit

Master's

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Bibliographic Details
Main Author:	NG KAR SIN
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2010
Subjects:	low power, instruction scheduling, computer architecture
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/14533
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-14533
record_format	dspace
spelling	sg-nus-scholar.10635-145332015-01-31T08:27:14Z A low power design for arithmetic and logic unit NG KAR SIN ELECTRICAL & COMPUTER ENGINEERING TAY TENG TIOW low power, instruction scheduling, computer architecture Master's MASTER OF ENGINEERING 2010-04-08T10:44:07Z 2010-04-08T10:44:07Z 2004-12-30 Thesis NG KAR SIN (2004-12-30). A low power design for arithmetic and logic unit. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/14533 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	low power, instruction scheduling, computer architecture
spellingShingle	low power, instruction scheduling, computer architecture NG KAR SIN A low power design for arithmetic and logic unit
description	Master's
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING NG KAR SIN
format	Theses and Dissertations
author	NG KAR SIN
author_sort	NG KAR SIN
title	A low power design for arithmetic and logic unit
title_short	A low power design for arithmetic and logic unit
title_full	A low power design for arithmetic and logic unit
title_fullStr	A low power design for arithmetic and logic unit
title_full_unstemmed	A low power design for arithmetic and logic unit
title_sort	low power design for arithmetic and logic unit
publishDate	2010
url	http://scholarbank.nus.edu.sg/handle/10635/14533
_version_	1681079042972844032

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