A DVS-based pipelined reconfigurable instruction memory

A DVS-based pipelined reconfigurable instruction memory

Proceedings - Design Automation Conference

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Bibliographic Details
Main Authors: Zhiguo, G., Mitra, T., Wong, W.-F.
Other Authors: COMPUTER SCIENCE
Format: Conference or Workshop Item
Published: 2013
Subjects:
Instruction cache
Low power
Reconfigurable memory
Online Access:http://scholarbank.nus.edu.sg/handle/10635/41512
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Institution: National University of Singapore

Internet

http://scholarbank.nus.edu.sg/handle/10635/41512

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