A DVS-based pipelined reconfigurable instruction memory

Proceedings - Design Automation Conference

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Bibliographic Details
Main Authors:	Zhiguo, G., Mitra, T., Wong, W.-F.
Other Authors:	COMPUTER SCIENCE
Format:	Conference or Workshop Item
Published:	2013
Subjects:	Instruction cache Low power Reconfigurable memory
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/41512
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-41512
record_format	dspace
spelling	sg-nus-scholar.10635-415122023-07-18T00:58:05Z A DVS-based pipelined reconfigurable instruction memory Zhiguo, G. Mitra, T. Wong, W.-F. COMPUTER SCIENCE Instruction cache Low power Reconfigurable memory Proceedings - Design Automation Conference 897-902 PDAWD 2013-07-04T08:29:16Z 2013-07-04T08:29:16Z 2009 Conference Paper Zhiguo, G., Mitra, T., Wong, W.-F. (2009). A DVS-based pipelined reconfigurable instruction memory. Proceedings - Design Automation Conference : 897-902. ScholarBank@NUS Repository. 9781605584973 0738100X http://scholarbank.nus.edu.sg/handle/10635/41512 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Instruction cache Low power Reconfigurable memory
spellingShingle	Instruction cache Low power Reconfigurable memory Zhiguo, G. Mitra, T. Wong, W.-F. A DVS-based pipelined reconfigurable instruction memory
description	Proceedings - Design Automation Conference
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE Zhiguo, G. Mitra, T. Wong, W.-F.
format	Conference or Workshop Item
author	Zhiguo, G. Mitra, T. Wong, W.-F.
author_sort	Zhiguo, G.
title	A DVS-based pipelined reconfigurable instruction memory
title_short	A DVS-based pipelined reconfigurable instruction memory
title_full	A DVS-based pipelined reconfigurable instruction memory
title_fullStr	A DVS-based pipelined reconfigurable instruction memory
title_full_unstemmed	A DVS-based pipelined reconfigurable instruction memory
title_sort	dvs-based pipelined reconfigurable instruction memory
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/41512
_version_	1772815389385818112

A DVS-based pipelined reconfigurable instruction memory

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