Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications

Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications

10.1109/TED.2014.2377751

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Bibliographic Details
Main Authors:	Seo, Yeongkyo, Fong, Xuanyao, Roy, Kaushik
Other Authors:	DEPT OF ELECTRICAL & COMPUTER ENGG
Published:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2019
Subjects:	Science & Technology Technology Physical Sciences Engineering, Electrical & Electronic Physics, Applied Engineering Physics Complementary polarizer magnetic domain walls multiterminal spin-transfer torque magnetic random access memory (STT-MRAM) on-chip memory oxidized magnetic coupling layer FAILURE DEVICE
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/156169
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Institution:	National University of Singapore

Description
Summary:	10.1109/TED.2014.2377751