Addressing performance bottlenecks for top-down engineered nanowire transistors

Ph.D

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Bibliographic Details
Main Author:	JIANG YU
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2010
Subjects:	Si Nanowire Transistors, SiGe Nanowire Transistors, Top-Down Process, Gate-All-Around, FUSI Gate Nanowire
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/17328
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-17328
record_format	dspace
spelling	sg-nus-scholar.10635-173282017-10-21T08:46:11Z Addressing performance bottlenecks for top-down engineered nanowire transistors JIANG YU ELECTRICAL & COMPUTER ENGINEERING CHAN SIU HUNG, DANIEL KWONG DIM-LEE Si Nanowire Transistors, SiGe Nanowire Transistors, Top-Down Process, Gate-All-Around, FUSI Gate Nanowire Ph.D DOCTOR OF PHILOSOPHY 2010-06-08T18:00:18Z 2010-06-08T18:00:18Z 2009-07-30 Thesis JIANG YU (2009-07-30). Addressing performance bottlenecks for top-down engineered nanowire transistors. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/17328 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	Si Nanowire Transistors, SiGe Nanowire Transistors, Top-Down Process, Gate-All-Around, FUSI Gate Nanowire
spellingShingle	Si Nanowire Transistors, SiGe Nanowire Transistors, Top-Down Process, Gate-All-Around, FUSI Gate Nanowire JIANG YU Addressing performance bottlenecks for top-down engineered nanowire transistors
description	Ph.D
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING JIANG YU
format	Theses and Dissertations
author	JIANG YU
author_sort	JIANG YU
title	Addressing performance bottlenecks for top-down engineered nanowire transistors
title_short	Addressing performance bottlenecks for top-down engineered nanowire transistors
title_full	Addressing performance bottlenecks for top-down engineered nanowire transistors
title_fullStr	Addressing performance bottlenecks for top-down engineered nanowire transistors
title_full_unstemmed	Addressing performance bottlenecks for top-down engineered nanowire transistors
title_sort	addressing performance bottlenecks for top-down engineered nanowire transistors
publishDate	2010
url	http://scholarbank.nus.edu.sg/handle/10635/17328
_version_	1681079475592232960

Addressing performance bottlenecks for top-down engineered nanowire transistors

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