AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES

AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES

Master's

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Bibliographic Details
Main Author: ZHAO BIN
Other Authors: ELECTRICAL ENGINEERING
Format: Theses and Dissertations
Published: 2020
Online Access:https://scholarbank.nus.edu.sg/handle/10635/177253
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Institution: National University of Singapore
id sg-nus-scholar.10635-177253
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spelling sg-nus-scholar.10635-1772532020-11-19T13:57:16Z AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES ZHAO BIN ELECTRICAL ENGINEERING SAMUDRA Master's MASTER OF ENGINEERING 2020-10-08T07:12:38Z 2020-10-08T07:12:38Z 1999 Thesis ZHAO BIN (1999). AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES. ScholarBank@NUS Repository. https://scholarbank.nus.edu.sg/handle/10635/177253 CCK BATCHLOAD 20201023
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
description Master's
author2 ELECTRICAL ENGINEERING
author_facet ELECTRICAL ENGINEERING
ZHAO BIN
format Theses and Dissertations
author ZHAO BIN
spellingShingle ZHAO BIN
AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
author_sort ZHAO BIN
title AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
title_short AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
title_full AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
title_fullStr AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
title_full_unstemmed AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES
title_sort accurate delay model for bicmos/cmos logic gates
publishDate 2020
url https://scholarbank.nus.edu.sg/handle/10635/177253
_version_ 1686108943793782784

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