An Energy-Efficient Processing Element Design for Coarse-Grained Reconfigurable Architecture on FPGA
International Conference on Communications, Circuits and Systems
Saved in:
Main Authors: | Lingzhi Su, Wang Ling Goh, Jingjing Lan, Vishnu P. Nambiar, Anh Tuan Do, Dassanayake Mudiyanselage Thilini Kaushalya Bandara, ADITI KULKARNI MOHITE, Wang Bo |
---|---|
Other Authors: | INSTITUTE OF SYSTEMS SCIENCE |
Format: | Article |
Published: |
IEEE
2022
|
Online Access: | https://scholarbank.nus.edu.sg/handle/10635/227228 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Architecture centric coarse-grained FPGA overlays
by: Abhishek Kumar Jain
Published: (2017) -
An Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable Architecture
by: Hung K. Nguyen, et al.
Published: (2017) -
Fine- and Coarse-Grain Reconfigurable Computing
by: Stamatis Vassiliadis, Dimitrios Soudris
Published: (2017) -
FPGA-based reconfigurable architecture for neural network
by: Sim, Ui Tek.
Published: (2008) -
REVAMP: A Systematic Framework for Heterogeneous CGRA Realization
by: Dassanayake Mudiyanselage Thilini Kaushalya Bandara, et al.
Published: (2022)