A framework to explore low-power architecture and variability-aware timing estimation of FPGAs

Master's

Saved in:

Bibliographic Details
Main Author:	LEE CHEE SING
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2011
Subjects:	FPGA, VPR, Affine, process variations, reconfigurable
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/23150
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-23150
record_format	dspace
spelling	sg-nus-scholar.10635-231502017-10-21T08:58:35Z A framework to explore low-power architecture and variability-aware timing estimation of FPGAs LEE CHEE SING ELECTRICAL & COMPUTER ENGINEERING HA YAJUN FPGA, VPR, Affine, process variations, reconfigurable Master's MASTER OF ENGINEERING 2011-06-10T18:03:07Z 2011-06-10T18:03:07Z 2007-05-18 Thesis LEE CHEE SING (2007-05-18). A framework to explore low-power architecture and variability-aware timing estimation of FPGAs. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/23150 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	FPGA, VPR, Affine, process variations, reconfigurable
spellingShingle	FPGA, VPR, Affine, process variations, reconfigurable LEE CHEE SING A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
description	Master's
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING LEE CHEE SING
format	Theses and Dissertations
author	LEE CHEE SING
author_sort	LEE CHEE SING
title	A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
title_short	A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
title_full	A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
title_fullStr	A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
title_full_unstemmed	A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
title_sort	framework to explore low-power architecture and variability-aware timing estimation of fpgas
publishDate	2011
url	http://scholarbank.nus.edu.sg/handle/10635/23150
_version_	1681080019393183744

A framework to explore low-power architecture and variability-aware timing estimation of FPGAs

Similar Items