DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm

DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm

10.1109/CICC53496.2022.9772786

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Bibliographic Details
Main Authors: Animesh Gupta, Viveka Konandur, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovettii, Massimo Alioto
Other Authors: ELECTRICAL AND COMPUTER ENGINEERING
Format: Conference or Workshop Item
Language:English
Published: IEEE 2023
Subjects:
data structures , neural nets
Online Access:https://scholarbank.nus.edu.sg/handle/10635/237282
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Institution: National University of Singapore
Language: English
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spelling sg-nus-scholar.10635-2372822024-04-15T05:56:54Z DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm Animesh Gupta Viveka Konandur Thoithoi Salam Saurabh Jain Orazio Aiello Paolo Crovettii Massimo Alioto ELECTRICAL AND COMPUTER ENGINEERING data structures , neural nets 10.1109/CICC53496.2022.9772786 DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm IEEE Custom Integrated Circuits Conference (CICC) 2023-02-14T09:58:02Z 2023-02-14T09:58:02Z 2022-04-24 Conference Paper Animesh Gupta, Viveka Konandur, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovettii, Massimo Alioto (2022-04-24). DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm IEEE Custom Integrated Circuits Conference (CICC). ScholarBank@NUS Repository. https://doi.org/10.1109/CICC53496.2022.9772786 978-1-6654-0756-4 2152-3630 https://scholarbank.nus.edu.sg/handle/10635/237282 en CC0 1.0 Universal http://creativecommons.org/publicdomain/zero/1.0/ IEEE
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
language English
topic data structures , neural nets
spellingShingle data structures , neural nets
Animesh Gupta
Viveka Konandur
Thoithoi Salam
Saurabh Jain
Orazio Aiello
Paolo Crovettii
Massimo Alioto
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
description 10.1109/CICC53496.2022.9772786
author2 ELECTRICAL AND COMPUTER ENGINEERING
author_facet ELECTRICAL AND COMPUTER ENGINEERING
Animesh Gupta
Viveka Konandur
Thoithoi Salam
Saurabh Jain
Orazio Aiello
Paolo Crovettii
Massimo Alioto
format Conference or Workshop Item
author Animesh Gupta
Viveka Konandur
Thoithoi Salam
Saurabh Jain
Orazio Aiello
Paolo Crovettii
Massimo Alioto
author_sort Animesh Gupta
title DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
title_short DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
title_full DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
title_fullStr DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
title_full_unstemmed DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
title_sort ddpmnet: all-digital pulse density-based dnn architecture with 228 gate equivalents/mac unit, 28-tops/w and 1.5-tops/mm2 in 40nm
publisher IEEE
publishDate 2023
url https://scholarbank.nus.edu.sg/handle/10635/237282
_version_ 1800915779712974848

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