An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning

10.1109/ISCAS48785.2022.9937891

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Bibliographic Details
Main Authors:	Nguyen, Thao NN, Veeravalli, Bharadwaj, Fong, Xuanyao
Other Authors:	ELECTRICAL AND COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	IEEE 2023
Subjects:	Science & Technology Technology Engineering, Electrical & Electronic Engineering Spiking Neural Networks Reconfigurable Computing Hardware Accelerator On-Chip Learning MODEL
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/245762
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-245762
record_format	dspace
spelling	sg-nus-scholar.10635-2457622024-04-16T10:49:32Z An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning Nguyen, Thao NN Veeravalli, Bharadwaj Fong, Xuanyao ELECTRICAL AND COMPUTER ENGINEERING Science & Technology Technology Engineering, Electrical & Electronic Engineering Spiking Neural Networks Reconfigurable Computing Hardware Accelerator On-Chip Learning MODEL 10.1109/ISCAS48785.2022.9937891 IEEE International Symposium on Circuits and Systems (ISCAS) 2022-May 2157-2161 2023-11-06T08:53:19Z 2023-11-06T08:53:19Z 2022 2023-11-05T09:03:52Z Conference Paper Nguyen, Thao NN, Veeravalli, Bharadwaj, Fong, Xuanyao (2022). An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning. IEEE International Symposium on Circuits and Systems (ISCAS) 2022-May : 2157-2161. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS48785.2022.9937891 9781665484855 0271-4302 https://scholarbank.nus.edu.sg/handle/10635/245762 IEEE Elements
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Science & Technology Technology Engineering, Electrical & Electronic Engineering Spiking Neural Networks Reconfigurable Computing Hardware Accelerator On-Chip Learning MODEL
spellingShingle	Science & Technology Technology Engineering, Electrical & Electronic Engineering Spiking Neural Networks Reconfigurable Computing Hardware Accelerator On-Chip Learning MODEL Nguyen, Thao NN Veeravalli, Bharadwaj Fong, Xuanyao An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
description	10.1109/ISCAS48785.2022.9937891
author2	ELECTRICAL AND COMPUTER ENGINEERING
author_facet	ELECTRICAL AND COMPUTER ENGINEERING Nguyen, Thao NN Veeravalli, Bharadwaj Fong, Xuanyao
format	Conference or Workshop Item
author	Nguyen, Thao NN Veeravalli, Bharadwaj Fong, Xuanyao
author_sort	Nguyen, Thao NN
title	An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
title_short	An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
title_full	An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
title_fullStr	An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
title_full_unstemmed	An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
title_sort	fpga-based co-processor for spiking neural networks with on-chip stdp-based learning
publisher	IEEE
publishDate	2023
url	https://scholarbank.nus.edu.sg/handle/10635/245762
_version_	1800915967787663360

An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning

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