Development of low on state resistance power devices
Master's
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sg-nus-scholar.10635-278212015-01-12T01:14:58Z Development of low on state resistance power devices GAN KIAN PAAU ELECTRICAL & COMPUTER ENGINEERING LIANG YUNG CHII SAMUDRA, GANESH S Superjunction devices, DMOS devices, power devices, ideal silicon limit, PFVDMOS, OBVDMOS Master's MASTER OF ENGINEERING 2011-10-18T18:01:38Z 2011-10-18T18:01:38Z 2004-01-11 Thesis GAN KIAN PAAU (2004-01-11). Development of low on state resistance power devices. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/27821 NOT_IN_WOS en |
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National University of Singapore |
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Singapore |
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ScholarBank@NUS |
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English |
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Superjunction devices, DMOS devices, power devices, ideal silicon limit, PFVDMOS, OBVDMOS |
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Superjunction devices, DMOS devices, power devices, ideal silicon limit, PFVDMOS, OBVDMOS GAN KIAN PAAU Development of low on state resistance power devices |
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Master's |
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ELECTRICAL & COMPUTER ENGINEERING |
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ELECTRICAL & COMPUTER ENGINEERING GAN KIAN PAAU |
format |
Theses and Dissertations |
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GAN KIAN PAAU |
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GAN KIAN PAAU |
title |
Development of low on state resistance power devices |
title_short |
Development of low on state resistance power devices |
title_full |
Development of low on state resistance power devices |
title_fullStr |
Development of low on state resistance power devices |
title_full_unstemmed |
Development of low on state resistance power devices |
title_sort |
development of low on state resistance power devices |
publishDate |
2011 |
url |
http://scholarbank.nus.edu.sg/handle/10635/27821 |
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