Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Ph.D

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Bibliographic Details
Main Author:	JAYASANKER JAYABALAN
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2011
Subjects:	Elastomer Mesh, Fine Pitch WLP, Mesh-Coplanar Probe, Multilayer, PEEC, MultiGigahertz test
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/27829
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-27829
record_format	dspace
spelling	sg-nus-scholar.10635-278292015-01-17T15:48:52Z Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package JAYASANKER JAYABALAN ELECTRICAL & COMPUTER ENGINEERING LEONG MOOK SENG OOI BAN LEONG Elastomer Mesh, Fine Pitch WLP, Mesh-Coplanar Probe, Multilayer, PEEC, MultiGigahertz test Ph.D DOCTOR OF PHILOSOPHY 2011-10-18T18:01:48Z 2011-10-18T18:01:48Z 2006-12-19 Thesis JAYASANKER JAYABALAN (2006-12-19). Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/27829 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	Elastomer Mesh, Fine Pitch WLP, Mesh-Coplanar Probe, Multilayer, PEEC, MultiGigahertz test
spellingShingle	Elastomer Mesh, Fine Pitch WLP, Mesh-Coplanar Probe, Multilayer, PEEC, MultiGigahertz test JAYASANKER JAYABALAN Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
description	Ph.D
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING JAYASANKER JAYABALAN
format	Theses and Dissertations
author	JAYASANKER JAYABALAN
author_sort	JAYASANKER JAYABALAN
title	Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
title_short	Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
title_full	Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
title_fullStr	Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
title_full_unstemmed	Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
title_sort	application of peec modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package
publishDate	2011
url	http://scholarbank.nus.edu.sg/handle/10635/27829
_version_	1681080629062533120

Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

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