Modeling and verifying hierarchical real-time systems using stateful timed CSP

10.1145/2430536.2430537

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Bibliographic Details
Main Authors:	Sun, J., Liu, Y., Dong, J.S., Shi, L., André, E.
Other Authors:	COMPUTER SCIENCE
Format:	Article
Published:	2013
Subjects:	Algorithms Languages Verification
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/38952
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-38952
record_format	dspace
spelling	sg-nus-scholar.10635-389522024-11-13T20:14:35Z Modeling and verifying hierarchical real-time systems using stateful timed CSP Sun, J. Liu, Y. Dong, J.S. Shi, L. André, E. COMPUTER SCIENCE Algorithms Languages Verification 10.1145/2430536.2430537 ACM Transactions on Software Engineering and Methodology 22 1 ATSME 2013-07-04T07:30:37Z 2013-07-04T07:30:37Z 2013 Article Sun, J., Liu, Y., Dong, J.S., Shi, L., André, E. (2013). Modeling and verifying hierarchical real-time systems using stateful timed CSP. ACM Transactions on Software Engineering and Methodology 22 (1). ScholarBank@NUS Repository. https://doi.org/10.1145/2430536.2430537 1049331X http://scholarbank.nus.edu.sg/handle/10635/38952 000330483700003 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Algorithms Languages Verification
spellingShingle	Algorithms Languages Verification Sun, J. Liu, Y. Dong, J.S. Shi, L. André, E. Modeling and verifying hierarchical real-time systems using stateful timed CSP
description	10.1145/2430536.2430537
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE Sun, J. Liu, Y. Dong, J.S. Shi, L. André, E.
format	Article
author	Sun, J. Liu, Y. Dong, J.S. Shi, L. André, E.
author_sort	Sun, J.
title	Modeling and verifying hierarchical real-time systems using stateful timed CSP
title_short	Modeling and verifying hierarchical real-time systems using stateful timed CSP
title_full	Modeling and verifying hierarchical real-time systems using stateful timed CSP
title_fullStr	Modeling and verifying hierarchical real-time systems using stateful timed CSP
title_full_unstemmed	Modeling and verifying hierarchical real-time systems using stateful timed CSP
title_sort	modeling and verifying hierarchical real-time systems using stateful timed csp
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/38952
_version_	1821220634896629760

Modeling and verifying hierarchical real-time systems using stateful timed CSP

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