Realizing live sequence charts in SystemVerilog
10.1109/TASE.2007.41
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2013
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sg-nus-scholar.10635-400092015-01-07T08:06:28Z Realizing live sequence charts in SystemVerilog Wang, H.H. Sun, J. Qin, S. Dong, J.S. COMPUTER SCIENCE 10.1109/TASE.2007.41 First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering, TASE '07 379-388 2013-07-04T07:54:37Z 2013-07-04T07:54:37Z 2007 Conference Paper Wang, H.H.,Sun, J.,Qin, S.,Dong, J.S. (2007). Realizing live sequence charts in SystemVerilog. First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering, TASE '07 : 379-388. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/TASE.2007.41" target="_blank">https://doi.org/10.1109/TASE.2007.41</a> 0769528562 http://scholarbank.nus.edu.sg/handle/10635/40009 NOT_IN_WOS Scopus |
| institution |
National University of Singapore |
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NUS Library |
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Singapore |
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ScholarBank@NUS |
| description |
10.1109/TASE.2007.41 |
| author2 |
COMPUTER SCIENCE |
| author_facet |
COMPUTER SCIENCE Wang, H.H. Sun, J. Qin, S. Dong, J.S. |
| format |
Conference or Workshop Item |
| author |
Wang, H.H. Sun, J. Qin, S. Dong, J.S. |
| spellingShingle |
Wang, H.H. Sun, J. Qin, S. Dong, J.S. Realizing live sequence charts in SystemVerilog |
| author_sort |
Wang, H.H. |
| title |
Realizing live sequence charts in SystemVerilog |
| title_short |
Realizing live sequence charts in SystemVerilog |
| title_full |
Realizing live sequence charts in SystemVerilog |
| title_fullStr |
Realizing live sequence charts in SystemVerilog |
| title_full_unstemmed |
Realizing live sequence charts in SystemVerilog |
| title_sort |
realizing live sequence charts in systemverilog |
| publishDate |
2013 |
| url |
http://scholarbank.nus.edu.sg/handle/10635/40009 |
| _version_ |
1681082194063261696 |