Processor caches built using multi-level spin-transfer torque RAM cells

10.1109/ISLPED.2011.5993610

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Bibliographic Details
Main Authors:	Chen, Y., Wong, W.-F., Li, H., Koh, C.-K.
Other Authors:	COMPUTER SCIENCE
Format:	Conference or Workshop Item
Published:	2013
Subjects:	MLC spintronic STT-RAM
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/40754
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-40754
record_format	dspace
spelling	sg-nus-scholar.10635-407542024-11-13T03:29:24Z Processor caches built using multi-level spin-transfer torque RAM cells Chen, Y. Wong, W.-F. Li, H. Koh, C.-K. COMPUTER SCIENCE MLC spintronic STT-RAM 10.1109/ISLPED.2011.5993610 Proceedings of the International Symposium on Low Power Electronics and Design 73-78 2013-07-04T08:11:34Z 2013-07-04T08:11:34Z 2011 Conference Paper Chen, Y.,Wong, W.-F.,Li, H.,Koh, C.-K. (2011). Processor caches built using multi-level spin-transfer torque RAM cells. Proceedings of the International Symposium on Low Power Electronics and Design : 73-78. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ISLPED.2011.5993610" target="_blank">https://doi.org/10.1109/ISLPED.2011.5993610</a> 9781612846590 15334678 http://scholarbank.nus.edu.sg/handle/10635/40754 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	MLC spintronic STT-RAM
spellingShingle	MLC spintronic STT-RAM Chen, Y. Wong, W.-F. Li, H. Koh, C.-K. Processor caches built using multi-level spin-transfer torque RAM cells
description	10.1109/ISLPED.2011.5993610
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE Chen, Y. Wong, W.-F. Li, H. Koh, C.-K.
format	Conference or Workshop Item
author	Chen, Y. Wong, W.-F. Li, H. Koh, C.-K.
author_sort	Chen, Y.
title	Processor caches built using multi-level spin-transfer torque RAM cells
title_short	Processor caches built using multi-level spin-transfer torque RAM cells
title_full	Processor caches built using multi-level spin-transfer torque RAM cells
title_fullStr	Processor caches built using multi-level spin-transfer torque RAM cells
title_full_unstemmed	Processor caches built using multi-level spin-transfer torque RAM cells
title_sort	processor caches built using multi-level spin-transfer torque ram cells
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/40754
_version_	1821208914756108288

Processor caches built using multi-level spin-transfer torque RAM cells

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