Temperature aware task sequencing and voltage scaling
10.1109/ICCAD.2008.4681641
Saved in:
Main Authors: | Jayaseelan, R., Mitra, T. |
---|---|
Other Authors: | COMPUTER SCIENCE |
Format: | Conference or Workshop Item |
Published: |
2013
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/40798 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Temperature aware scheduling for embedded processors
by: Jayaseelan, R., et al.
Published: (2013) -
Temperature aware scheduling for embedded processors
by: Jayaseelan, R., et al.
Published: (2013) -
Shared cache aware task mapping for WCRT minimization
by: Ding, H., et al.
Published: (2014) -
Customized MPSoC synthesis for task sequence
by: Chen, L., et al.
Published: (2013) -
A hybrid local-global approach for multi-core thermal management
by: Jayaseelan, R., et al.
Published: (2013)