Modeling shared cache and bus in multi-cores for timing analysis

10.1145/1811212.1811220

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Bibliographic Details
Main Authors:	Chattopadhyay, S., Roychoudhury, A., Mitra, T.
Other Authors:	COMPUTER SCIENCE
Format:	Conference or Workshop Item
Published:	2013
Subjects:	Multi-core Shared bus Shared cache WCET
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/41932
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-41932
record_format	dspace
spelling	sg-nus-scholar.10635-419322023-07-18T00:57:58Z Modeling shared cache and bus in multi-cores for timing analysis Chattopadhyay, S. Roychoudhury, A. Mitra, T. COMPUTER SCIENCE Multi-core Shared bus Shared cache WCET 10.1145/1811212.1811220 Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010 2013-07-04T08:39:18Z 2013-07-04T08:39:18Z 2010 Conference Paper Chattopadhyay, S., Roychoudhury, A., Mitra, T. (2010). Modeling shared cache and bus in multi-cores for timing analysis. Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010. ScholarBank@NUS Repository. https://doi.org/10.1145/1811212.1811220 9781450300841 http://scholarbank.nus.edu.sg/handle/10635/41932 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Multi-core Shared bus Shared cache WCET
spellingShingle	Multi-core Shared bus Shared cache WCET Chattopadhyay, S. Roychoudhury, A. Mitra, T. Modeling shared cache and bus in multi-cores for timing analysis
description	10.1145/1811212.1811220
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE Chattopadhyay, S. Roychoudhury, A. Mitra, T.
format	Conference or Workshop Item
author	Chattopadhyay, S. Roychoudhury, A. Mitra, T.
author_sort	Chattopadhyay, S.
title	Modeling shared cache and bus in multi-cores for timing analysis
title_short	Modeling shared cache and bus in multi-cores for timing analysis
title_full	Modeling shared cache and bus in multi-cores for timing analysis
title_fullStr	Modeling shared cache and bus in multi-cores for timing analysis
title_full_unstemmed	Modeling shared cache and bus in multi-cores for timing analysis
title_sort	modeling shared cache and bus in multi-cores for timing analysis
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/41932
_version_	1772815407791472640

Modeling shared cache and bus in multi-cores for timing analysis

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