Modeling shared cache and bus in multi-cores for timing analysis

• Main Authors: Chattopadhyay, S., Roychoudhury, A., Mitra, T.
• Other Authors: COMPUTER SCIENCE
• Format: Conference or Workshop Item
• Published: 2013
• Subjects: Multi-core; Shared bus; Shared cache; WCET
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/41932
• Institution: National University of Singapore

10.1145/1811212.1811220