An automatic mapping from Statecharts to Verilog

Lecture Notes in Computer Science

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Bibliographic Details
Main Authors:	Tran, V.-A.V., Qin, S., Chin, W.N.
Other Authors:	SINGAPORE-MIT ALLIANCE
Format:	Conference or Workshop Item
Published:	2013
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/43326
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-43326
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spelling	sg-nus-scholar.10635-433262015-01-18T06:35:18Z An automatic mapping from Statecharts to Verilog Tran, V.-A.V. Qin, S. Chin, W.N. SINGAPORE-MIT ALLIANCE COMPUTER SCIENCE Lecture Notes in Computer Science 3407 187-203 2013-07-23T09:31:03Z 2013-07-23T09:31:03Z 2005 Conference Paper Tran, V.-A.V.,Qin, S.,Chin, W.N. (2005). An automatic mapping from Statecharts to Verilog. Lecture Notes in Computer Science 3407 : 187-203. ScholarBank@NUS Repository. 03029743 http://scholarbank.nus.edu.sg/handle/10635/43326 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Lecture Notes in Computer Science
author2	SINGAPORE-MIT ALLIANCE
author_facet	SINGAPORE-MIT ALLIANCE Tran, V.-A.V. Qin, S. Chin, W.N.
format	Conference or Workshop Item
author	Tran, V.-A.V. Qin, S. Chin, W.N.
spellingShingle	Tran, V.-A.V. Qin, S. Chin, W.N. An automatic mapping from Statecharts to Verilog
author_sort	Tran, V.-A.V.
title	An automatic mapping from Statecharts to Verilog
title_short	An automatic mapping from Statecharts to Verilog
title_full	An automatic mapping from Statecharts to Verilog
title_fullStr	An automatic mapping from Statecharts to Verilog
title_full_unstemmed	An automatic mapping from Statecharts to Verilog
title_sort	automatic mapping from statecharts to verilog
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/43326
_version_	1681082762728046592

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