Yield optimization by design centering & worst-case distance analysis
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Saved in:
Main Authors: | Samudra, G.S., Chen, H.M., Chan, D.S.H., Ibrahim, Yaacob |
---|---|
Other Authors: | ELECTRICAL ENGINEERING |
Format: | Article |
Published: |
2014
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/50611 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Yield optimization by design centering & worst-case distance analysis
by: Samudra, G.S., et al.
Published: (2014) -
Circuit performance and yield optimization with worst-case and Monte Carlo analyses
by: Lan, C.S., et al.
Published: (2014) -
Performance spread optimization of MOS VLSI circuit by statistical parameter design
by: Chen, H.M., et al.
Published: (2014) -
Performance spread optimization of MOS VLSI circuit by statistical parameter design
by: Chen, H.M., et al.
Published: (2014) -
Global optimization for digital MOS circuits performance
by: Chen, H.M., et al.
Published: (2014)