Via design optimization for high speed device packaging

Via design optimization for high speed device packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

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Bibliographic Details
Main Authors: Low, Hong-Guan, Iyer, Mahadevan K., Ooi, Ban-Leong, Leong, Mook-Seng
Other Authors: INSTITUTE OF MICROELECTRONICS
Format: Article
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/62927
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Institution: National University of Singapore
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Summary:Proceedings of the Electronic Packaging Technology Conference, EPTC

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