Via design optimization for high speed device packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Saved in:

Bibliographic Details
Main Authors:	Low, Hong-Guan, Iyer, Mahadevan K., Ooi, Ban-Leong, Leong, Mook-Seng
Other Authors:	INSTITUTE OF MICROELECTRONICS
Format:	Article
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/62927
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

id	sg-nus-scholar.10635-62927
record_format	dspace
spelling	sg-nus-scholar.10635-629272015-01-30T17:27:54Z Via design optimization for high speed device packaging Low, Hong-Guan Iyer, Mahadevan K. Ooi, Ban-Leong Leong, Mook-Seng INSTITUTE OF MICROELECTRONICS ELECTRICAL ENGINEERING Proceedings of the Electronic Packaging Technology Conference, EPTC 112-118 00313 2014-06-17T06:56:25Z 2014-06-17T06:56:25Z 1998 Article Low, Hong-Guan,Iyer, Mahadevan K.,Ooi, Ban-Leong,Leong, Mook-Seng (1998). Via design optimization for high speed device packaging. Proceedings of the Electronic Packaging Technology Conference, EPTC : 112-118. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/62927 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Proceedings of the Electronic Packaging Technology Conference, EPTC
author2	INSTITUTE OF MICROELECTRONICS
author_facet	INSTITUTE OF MICROELECTRONICS Low, Hong-Guan Iyer, Mahadevan K. Ooi, Ban-Leong Leong, Mook-Seng
format	Article
author	Low, Hong-Guan Iyer, Mahadevan K. Ooi, Ban-Leong Leong, Mook-Seng
spellingShingle	Low, Hong-Guan Iyer, Mahadevan K. Ooi, Ban-Leong Leong, Mook-Seng Via design optimization for high speed device packaging
author_sort	Low, Hong-Guan
title	Via design optimization for high speed device packaging
title_short	Via design optimization for high speed device packaging
title_full	Via design optimization for high speed device packaging
title_fullStr	Via design optimization for high speed device packaging
title_full_unstemmed	Via design optimization for high speed device packaging
title_sort	via design optimization for high speed device packaging
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/62927
_version_	1681085865209626624

Via design optimization for high speed device packaging

Similar Items