VLSI circuits for decomposing binary integers into signed power-of-two terms
Proceedings - IEEE International Symposium on Circuits and Systems
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Published: |
2014
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| Online Access: | http://scholarbank.nus.edu.sg/handle/10635/72990 |
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| Institution: | National University of Singapore |