FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network

10.1109/TCSII.2012.2234891

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Bibliographic Details
Main Authors:	Wang, Y., Ha, Y.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	Advanced encryption standard (AES) differential power analysis (DPA) field programmable gate array (FPGA) masking storage area network (SAN)
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/82381
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-82381
record_format	dspace
spelling	sg-nus-scholar.10635-823812023-10-25T21:06:44Z FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network Wang, Y. Ha, Y. ELECTRICAL & COMPUTER ENGINEERING Advanced encryption standard (AES) differential power analysis (DPA) field programmable gate array (FPGA) masking storage area network (SAN) 10.1109/TCSII.2012.2234891 IEEE Transactions on Circuits and Systems II: Express Briefs 60 1 36-40 2014-10-07T04:28:42Z 2014-10-07T04:28:42Z 2013 Article Wang, Y., Ha, Y. (2013). FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network. IEEE Transactions on Circuits and Systems II: Express Briefs 60 (1) : 36-40. ScholarBank@NUS Repository. https://doi.org/10.1109/TCSII.2012.2234891 15497747 http://scholarbank.nus.edu.sg/handle/10635/82381 000316262000008 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Advanced encryption standard (AES) differential power analysis (DPA) field programmable gate array (FPGA) masking storage area network (SAN)
spellingShingle	Advanced encryption standard (AES) differential power analysis (DPA) field programmable gate array (FPGA) masking storage area network (SAN) Wang, Y. Ha, Y. FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
description	10.1109/TCSII.2012.2234891
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Wang, Y. Ha, Y.
format	Article
author	Wang, Y. Ha, Y.
author_sort	Wang, Y.
title	FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
title_short	FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
title_full	FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
title_fullStr	FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
title_full_unstemmed	FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network
title_sort	fpga-based 40.9-gbits/s masked aes with area optimization for storage area network
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/82381
_version_	1781784123433549824

FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network

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