FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network

FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network

10.1109/TCSII.2012.2234891

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Bibliographic Details
Main Authors:	Wang, Y., Ha, Y.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	Advanced encryption standard (AES) differential power analysis (DPA) field programmable gate array (FPGA) masking storage area network (SAN)
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/82381
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

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