Decoding of DBEC-TBED Reed-Solomon Codes
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are orga...
Saved in:
Main Authors: | DENG, Robert H., COSTELLO, Daniel J. Jr. |
---|---|
Format: | text |
Language: | English |
Published: |
Institutional Knowledge at Singapore Management University
1987
|
Subjects: | |
Online Access: | https://ink.library.smu.edu.sg/sis_research/149 https://ink.library.smu.edu.sg/context/sis_research/article/1148/viewcontent/Decoding_DBEC_TBED_1987.pdf |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Singapore Management University |
Language: | English |
Similar Items
-
On transformed folded shortened reed-solomon codes for the correction of phased bursts
by: Jianwen, Z., et al.
Published: (2014) -
Contributions to folded reed-solomon codes for burst error correction
by: ZHANG JIANWEN
Published: (2010) -
Multistage list decoding of generalized Reed-Solomon codes over Galois rings
by: Armand, M.A., et al.
Published: (2014) -
Interleaved Reed-Solomon codes versus interleaved Hermitian codes
by: Armand, M.A.
Published: (2014) -
Repair of Reed-Solomon codes in the presence of erroneous nodes
by: Kruglik, Stanislav, et al.
Published: (2023)