Modeling and verifying hierarchical real-time systems using stateful timed CSP

• المؤلفون الرئيسيون: SUN, Jun, LIU, Yang, DONG, Jin Song, LIU, Yan, SHI, Ling, ANDRÉ, Étienne
• التنسيق: text
• اللغة: English
• منشور في: Institutional Knowledge at Singapore Management University 2013
• الموضوعات: Algorithms; Languages; Verification; Programming Languages and Compilers; Software Engineering
• الوصول للمادة أونلاين: https://ink.library.smu.edu.sg/sis_research/4995; https://ink.library.smu.edu.sg/context/sis_research/article/5998/viewcontent/2430536.2430537.pdf

Modeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a langu...