Modeling and verifying hierarchical real-time systems using stateful timed CSP

Modeling and verifying hierarchical real-time systems using stateful timed CSP

Modeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a langu...

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Bibliographic Details
Main Authors: SUN, Jun, LIU, Yang, DONG, Jin Song, LIU, Yan, SHI, Ling, ANDRÉ, Étienne
Format: text
Language:English
Published: Institutional Knowledge at Singapore Management University 2013
Subjects:
Algorithms
Languages
Verification
Programming Languages and Compilers
Software Engineering
Online Access:https://ink.library.smu.edu.sg/sis_research/4995
https://ink.library.smu.edu.sg/context/sis_research/article/5998/viewcontent/2430536.2430537.pdf
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Institution: Singapore Management University
Language: English

Internet

https://ink.library.smu.edu.sg/sis_research/4995
https://ink.library.smu.edu.sg/context/sis_research/article/5998/viewcontent/2430536.2430537.pdf

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