Parameter synthesis for hierarchical concurrent real-time systems
Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering...
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sg-smu-ink.sis_research-60232020-03-12T09:06:12Z Parameter synthesis for hierarchical concurrent real-time systems ANDRÉ, Étienne LIU, Yang SUN, Jun DONG, Jin Song Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesize a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed CSP, a language capable of specifying hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present an algorithm for efficient parameter synthesis that behaves well in practice. 2012-07-01T07:00:00Z text application/pdf https://ink.library.smu.edu.sg/sis_research/5020 info:doi/10.1109/ICECCS20050.2012.6299220 https://ink.library.smu.edu.sg/context/sis_research/article/6023/viewcontent/2014_Parameter_Synthesis_for_Hierarchical_Concurrent_Real_time_Systems__2_.pdf http://creativecommons.org/licenses/by-nc-nd/4.0/ Research Collection School Of Computing and Information Systems eng Institutional Knowledge at Singapore Management University Real-time specification Parametric timed verification Model checking Robustness Software Engineering |
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Real-time specification Parametric timed verification Model checking Robustness Software Engineering ANDRÉ, Étienne LIU, Yang SUN, Jun DONG, Jin Song Parameter synthesis for hierarchical concurrent real-time systems |
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Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesize a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed CSP, a language capable of specifying hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present an algorithm for efficient parameter synthesis that behaves well in practice. |
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text |
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ANDRÉ, Étienne LIU, Yang SUN, Jun DONG, Jin Song |
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ANDRÉ, Étienne LIU, Yang SUN, Jun DONG, Jin Song |
author_sort |
ANDRÉ, Étienne |
title |
Parameter synthesis for hierarchical concurrent real-time systems |
title_short |
Parameter synthesis for hierarchical concurrent real-time systems |
title_full |
Parameter synthesis for hierarchical concurrent real-time systems |
title_fullStr |
Parameter synthesis for hierarchical concurrent real-time systems |
title_full_unstemmed |
Parameter synthesis for hierarchical concurrent real-time systems |
title_sort |
parameter synthesis for hierarchical concurrent real-time systems |
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Institutional Knowledge at Singapore Management University |
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2012 |
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https://ink.library.smu.edu.sg/sis_research/5020 https://ink.library.smu.edu.sg/context/sis_research/article/6023/viewcontent/2014_Parameter_Synthesis_for_Hierarchical_Concurrent_Real_time_Systems__2_.pdf |
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