Verifying stateful timed CSP using implicit clocks and zone abstraction
In this work, we study model checking of compositional real-time systems. A system is modeled using mutable data variables as well as a compositional timed process. Instead of explicitly manipulating clock variables, a number of compositional timed behavioral patterns are used to capture quantitativ...
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| Main Authors: | , , , |
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| Format: | text |
| Language: | English |
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Institutional Knowledge at Singapore Management University
2009
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| Subjects: | |
| Online Access: | https://ink.library.smu.edu.sg/sis_research/5042 https://ink.library.smu.edu.sg/context/sis_research/article/6045/viewcontent/verifying.pdf |
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| Institution: | Singapore Management University |
| Language: | English |
| Summary: | In this work, we study model checking of compositional real-time systems. A system is modeled using mutable data variables as well as a compositional timed process. Instead of explicitly manipulating clock variables, a number of compositional timed behavioral patterns are used to capture quantitative timing requirements, e.g. delay, timeout, deadline, timed interrupt, etc. A fully automated abstraction technique is developed to build an abstract finite state machine from the model. The idea is to dynamically create/delete clocks, and maintain/solve a constraint on the clocks. The abstract machine weakly bi-simulates the model and, therefore, LTL model checking or trace-refinement checking are sound and complete. We enhance our home-grown PAT model checker with the technique and show its usability via the verification of benchmark systems. |
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