Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+...

by Wang, G.H., Toh, E.-H., Wang, X., Seng, D.H.L., Tripathy, S., Osipowicz, T., Tau, K.C., Samudra, G., Yeo, Y.-C.
Published 2014

Silicon-germanium-tin (SiGeSn) source and drain stressors formed by Sn implant and laser annealing for strained silicon-germanium channel P-MOSFETs

by Wang, G.H., Toh, E.-H., Wang, X., Seng, D.H.L., Tripathy, S., Osipowicz, T., Chan, T.K., Hoe, K.M., Balakumar, S., Tung, C.H., Lo, G.-Q., Samudra, G., Yeo, Y.-C.
Published 2014

Role of AlxGa1-xAs buffer layer in heterogeneous integration of GaAs/Ge

by Chia, C.K., Dalapati, G.K., Chai, Y., Lu, S.L., He, W., Dong, J.R., Seng, D.H.L., Hui, H.K., Wong, A.S.W., Lau, A.J.Y., Cheng, Y.B., Chi, D.Z., Zhu, Z., Yeo, Y.C., Xu, Z., Yoon, S.F.
Published 2014