TRANSACTION LEVEL MODELING FOR EARLY VERIFICATION ON HARDWARE EMBEDDED SYSTEM DESIGN

TRANSACTION LEVEL MODELING FOR EARLY VERIFICATION ON HARDWARE EMBEDDED SYSTEM DESIGN

Abstract—Time-to-market pressure and productivity gap are two factors that encourage the Electronic Design Automation (EDA) industry vendor and researcher of embedded system to enhanche embedded system design method. Current embedded system design approach, Register Transfer Level (RTL), is not s...

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Bibliographic Details
Main Author: ABDUROHMAN (NIM : 33207001); Tim Pembimbing : Prof. Dr.Ir. Kuspriyanto; Dr. Ir. Sarwono Sutikn, MAMAN
Format: Dissertations
Language:Indonesia
Online Access:https://digilib.itb.ac.id/gdl/view/16340
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Institution: Institut Teknologi Bandung
Language: Indonesia

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https://digilib.itb.ac.id/gdl/view/16340

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