TRANSACTION LEVEL MODELING FOR EARLY VERIFICATION ON HARDWARE EMBEDDED SYSTEM DESIGN

• Main Author: ABDUROHMAN (NIM : 33207001); Tim Pembimbing : Prof. Dr.Ir. Kuspriyanto; Dr. Ir. Sarwono Sutikn, MAMAN
• Format: Dissertations
• Language: Indonesia
• Online Access: https://digilib.itb.ac.id/gdl/view/16340
• Institution: Institut Teknologi Bandung

Abstract—Time-to-market pressure and productivity gap are two factors that encourage the Electronic Design Automation (EDA) industry vendor and researcher of embedded system to enhanche embedded system design method. Current embedded system design approach, Register Transfer Level (RTL), is not sufficient to meet the embedded system design necessity. Its needs a new design methodology that enhance design process performance. This dissertation addresses the performance improvement of design process by making the new design flow for embedded system hardware design at higher abstraction level. Increasing model abstraction advances speed design process that meet the embedded system necessity. The method used in this modeling is Transaction Level Modeling (TLM). This dissertation proposses the new design flow on Transaction Level Modeling (TLM) for early verification purpose on embedded system design. Design process can be divided into two stages : the first is TLM modeling and verification process. Detailed RTL model done after design requirement fulfilment. This modeling is used to know fungtionality fulfilment at early stage. The result of this dissertation is parameterized by accuration rate comparison between transaction level model and RTL model. Parameters used in this research are design process performance, design accuration, functionality accuration and simulation speed. In addition to new design flow, it was propossed the new standard procedure for model transformation process. This procedure is a processing standard to model hardware embedded system. On transformation process from TLM model to RTL there is a sistematic stages with case study tranformation using Avalon and Wishbon bus. Both buses are System on Chip (SoC) buses that connects many master components to slave components on SoC system. Transformation result of RTL model then compared to TLM model to measure the modeling performance. <br /> <br /> The results on this dissertaion show there was a performance increasing on TLM design process compared to RTL. The result of experiment on Avalon bus are for 3-modules was 1,03, 4-modules was 1,47 and 5-modules was 1,69. The result of experiment on Wishbone bus are for 3-modules was 1,12, 4- modules was 1,17 and 5- modules was 1,34. This enhancement shows the trend to better condition. More complex designed system will make better design performance. On TLM model design, system bus is designed as a transaction channel between many masters and slaves that be controlled by arbiter. The addition to masters and slaves are not affected to the bus and arbiter processes. In contrast, on RTL model design, system bus depends on number of master and slave components. The addition of master and slave components needs the addition of system bus components. This condition is bringing on TLM model design process faster than RTL model design on system with number of component more than two. It can be concluded that design process of embedded system hardware using TLM design flow better than RTL level design with the best performance enhancement is 1,69. This performance enhancement means that using new design methodology 1,69 times faster than RTL design. The new TLM design flow can be used on complex system with many components that intearct each other with arbitration process in it. TLM-RTL model transformation method, Incremental Model Transformation (IMT), using TR-Model Communicator (TMC) can speed transformation process up with verification process on every stages. RTL bus synthesis process produces RTL bus with topology and arbitration customization.