PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM
<b> Abstract :</b><p align=\"justify\"> <br /> A new parallel architecture concept for image processing has been successfully developed. This architecture named LAPCAM (Linear Array of Processors with Content Addressable Memories). <br /> LAPCAM has three m...
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| Format: | Theses |
| Language: | Indonesia |
| Online Access: | https://digilib.itb.ac.id/gdl/view/5327 |
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| Institution: | Institut Teknologi Bandung |
| Language: | Indonesia |
| Summary: | <b> Abstract :</b><p align=\"justify\"> <br />
A new parallel architecture concept for image processing has been successfully developed. This architecture named LAPCAM (Linear Array of Processors with Content Addressable Memories). <br />
LAPCAM has three main components: Processor Element (PE), Multi-mode Access Memory (MAM) and Orthogonal Addressable Crossbar (OAC).<p align=\"justify\"> Discovering a new type of memory and interconnection network called MAM (Multi-mode Access Memory) and OAC (Orthogonal Addressable Crossbar) respectively, LAPCAM finally develops as an optimal parallel architecture.<p align=\"justify\"> <br />
This thesis presents: <br />
1. Design a RISC processor element for LAPCAM architecture. <br />
2. Develop the design in VHDL (VHSIC Hardware Description Language). <br />
3. Verify the design by simulation using Software Max+Plus II from ALTERA. <br />
4. Evaluate the simulation result. <br />
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