PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM
<b> Abstract :</b><p align=\"justify\"> <br /> A new parallel architecture concept for image processing has been successfully developed. This architecture named LAPCAM (Linear Array of Processors with Content Addressable Memories). <br /> LAPCAM has three m...
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id-itb.:53272006-04-19T09:00:54ZPERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM Wahyu Tri Hartono, R. Indonesia Theses INSTITUT TEKNOLOGI BANDUNG https://digilib.itb.ac.id/gdl/view/5327 <b> Abstract :</b><p align=\"justify\"> <br /> A new parallel architecture concept for image processing has been successfully developed. This architecture named LAPCAM (Linear Array of Processors with Content Addressable Memories). <br /> LAPCAM has three main components: Processor Element (PE), Multi-mode Access Memory (MAM) and Orthogonal Addressable Crossbar (OAC).<p align=\"justify\"> Discovering a new type of memory and interconnection network called MAM (Multi-mode Access Memory) and OAC (Orthogonal Addressable Crossbar) respectively, LAPCAM finally develops as an optimal parallel architecture.<p align=\"justify\"> <br /> This thesis presents: <br /> 1. Design a RISC processor element for LAPCAM architecture. <br /> 2. Develop the design in VHDL (VHSIC Hardware Description Language). <br /> 3. Verify the design by simulation using Software Max+Plus II from ALTERA. <br /> 4. Evaluate the simulation result. <br /> <br /> text |
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<b> Abstract :</b><p align=\"justify\"> <br />
A new parallel architecture concept for image processing has been successfully developed. This architecture named LAPCAM (Linear Array of Processors with Content Addressable Memories). <br />
LAPCAM has three main components: Processor Element (PE), Multi-mode Access Memory (MAM) and Orthogonal Addressable Crossbar (OAC).<p align=\"justify\"> Discovering a new type of memory and interconnection network called MAM (Multi-mode Access Memory) and OAC (Orthogonal Addressable Crossbar) respectively, LAPCAM finally develops as an optimal parallel architecture.<p align=\"justify\"> <br />
This thesis presents: <br />
1. Design a RISC processor element for LAPCAM architecture. <br />
2. Develop the design in VHDL (VHSIC Hardware Description Language). <br />
3. Verify the design by simulation using Software Max+Plus II from ALTERA. <br />
4. Evaluate the simulation result. <br />
<br />
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format |
Theses |
author |
Wahyu Tri Hartono, R. |
spellingShingle |
Wahyu Tri Hartono, R. PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
author_facet |
Wahyu Tri Hartono, R. |
author_sort |
Wahyu Tri Hartono, R. |
title |
PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
title_short |
PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
title_full |
PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
title_fullStr |
PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
title_full_unstemmed |
PERANCANGAN DAN SIMULASI VHDL RISC PROCESSOR ELEMENT UNTUK ARSITEKTUR PARALEL PENGOLAHAN CITRA LAPCAM |
title_sort |
perancangan dan simulasi vhdl risc processor element untuk arsitektur paralel pengolahan citra lapcam |
url |
https://digilib.itb.ac.id/gdl/view/5327 |
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1820663654593331200 |