Taguchi modeling of process parameters in vdg-mosfet device for higher ION/IOFF ratio

• Main Authors: Kaharudin, K.E., Salehuddin, F., Hamidon, A.H., Aziz, M.N.I.A., Ahmad, I.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5200
• Institution: Universiti Tenaga Nasional

The miniaturization in the size of planar MOSFET device seems to be limited when it reaches to 22nm technology node. In this paper, the vertical double gate architecture of MOSFET device with ultrathin Si- pillar was introduced by keeping both silicon dioxide (SiO2) and polysilicon as the main materials. The proposed MOSFET architecture was known as Ultrathin Pillar Vertical Double Gate (VDG) MOSFET device and it was integrated with polysilicon-on-insulator (PSOI) technology for a superior electrical performance. The virtual device fabrication and characterization were done by using ATHENA and ATLAS modules of SILVACO Internationals. The process parameters of the device were then optimized by utilizing L27 orthogonal array of Taguchi method in order to obtain the highest value of drive current (ION) and the lowest value of leakage current (IOFF). The highest value of ION/IOFF ratio after an optimization approach was observed to be 2.154x 1012. © 2015 Penerbit UTM Press. All rights reserved.