Taguchi modeling of process parameters in vdg-mosfet device for higher ION/IOFF ratio

• Main Authors: Kaharudin, K.E., Salehuddin, F., Hamidon, A.H., Aziz, M.N.I.A., Ahmad, I.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5200
• Institution: Universiti Tenaga Nasional

The miniaturization in the size of planar MOSFET device seems to be limited when it reaches to 22nm technology node. In this paper, the vertical double gate architecture of MOSFET device with ultrathin Si- pillar was introduced by keeping both silicon dioxide (SiO2) and polysilicon as the main mater...