Design and optimization of 22nm NMOS transistor

• Main Authors: Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Shaari, S., Elgomati, H.A., Majlis, B.Y., Salehuddin, F.
• Published: 2017
• Online Access: http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5228
• Institution: Universiti Tenaga Nasional

In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. Taguchi's experimental design strategy was implemented with the L9 orthogonal array for conducting 36 simulation runs. The simulators were used for computing V th values for each row of the L9 array with 4 combinations of the 2 noise factors. The objective function for minimizing the variance in V th is achieved using Taguchi's nominal-the-best signal-to-noise ratio (SNR). Analysis of Mean (ANOM) was used to determine the best settings for the process parameters whereas. Analysis of variance (ANOVA) was used to reduce the variability of Vth. The best settings were used for verification experiments and the results show V th values with the least variance and that the mean value can be adjusted to 0.306V ±0.027 for the 22nm NMOS, which is well within the ITRS2011 specifications.